Lifetime Validation of Digital Systems via Fault Modeling and Test Generation

LIFETIME VALIDATION OF DIGITAL SYSTEMS VIA FAULT MODELING AND TEST GENERATION by Hussain Said Al-Asaad Chair: John P. Hayes The steady growth in the complexity of digital systems demands more efficient algorithms and tools for design verification and testing. Design verification is becoming increasingly important due to shorter design cycles and the high cost of system failures. During normal operation, digital systems are subject to operational faults, which require regular on-line testing in the field, especially for high-availability and safety-critical applications. Fabrication fault testing has a well-developed methodology that can, in principle, be adapted for efficient design validation and on-line testing. This thesis investigates a comprehensive “lifetime” validation approach that uses fabrication fault testing and simulation techniques, and accounts for design errors, fabrication faults, and operational faults. The validation is achieved by the following sequence of steps: (1) explicit error and fault modeling, (2) model-directed test generation, and (3) test application. We first present a hardware design validation methodology that follows the foregoing validation approach. We analyze the gate-level design error models used in prior research and show how to map them into single stuck-line (SSL) faults. We then describe an extensive set of experiments, which demonstrate that high coverage of the modeled gate-level errors can be achieved with small test sets obtained with standard test generation and simulation tools for fabrication faults. Due to the absence of published error data, we have systematically collected design errors from a number of microprocessor design projects, and used them to construct high-level error models suitable for design validation. Experimental results indicate that very high coverage of actual design errors can be obtained with test sets that are complete for a small number of design error models. We further present a new error model for control errors in microprocessors and a validation approach